SVA: throughout corner case | sig1 must be stable throughout sig2

SystemVerilog
, ,
2 
property sig1_stable_throughout_sig2 (logic sig1, sig2);
     disable iff (!sig2)
     $rose(sig2) |=> $stable(sig1) throughout !sig2[->1];
endproperty //sig1_stable_throughout_sig2

Disabling the assertion when sig2 goes down seems to do the trick. Is this approach correct?

Thanks
-Ankit