SVA syntax

SystemVerilog
, ,
1

hi,

  1. in the following sequence:
a ##1 b[m:n] ##1 c

does this imply

!c

during the time that:

 b[m:n] ##1

?

  1. if so, is this true to other SVA tasks, for example:
a ##1 b[->1] ##1 c

implies:

!c

during the time that:

 b[->1] ##1

?

thanks

2

In reply to gidon:

No it does not imply anything. Only that the condition of each Boolean expression must be true at the specified time within the sequence