In reply to ben@SystemVerilog.us:
On the $fell(rst_n) (rst_n is active lo) I can see your point.
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I think we’re talking about different things here. For an active low reset, $fell(…) is true when the reset starts being applied. $rose(…) is true when coming out of reset. My intent wasn’t to check that when going into reset some condition was true. The intent was to check what happens when coming out of reset.
Using $rose(…) would catch the bug you described.