Would this solution work for you?
always begin
automatic bit loc_sig;
@(start_ev) loc_sig =sig;
fork
@(end_ev)
if (loc_sig != sig) $display("a t=%t, error in sig @end_ev", $time);
@(sig)
if (loc_sig != sig) $display("at t=%t, error in sig @sig", $time);
join_any
end
Note: Could use immediate assertions instead of the “if” statements.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115