In reply to ben@SystemVerilog.us:
It’s my mistake, I formulated my question badly… Actually I wanted to ask about the difference between the ##[1:3]a and *a[1:3] in assertions…
As for a[*1:3], does it means that statement ‘a’ should be repeated for 1, 2, or 3 cycles?
Will it the same as writing always(a)[*1:3]?
As for ##[1:3]a, does it mean that statement ‘a’ should be delayed for 1, 2 or 3 cycles?