[SVA] signal rises and stays stable check -> how to write an assertion?

SystemVerilog
14

In reply to dmitryl:

  • ##[1:3]a is same as 1’b1 ##[1:3]a, and tha is a clock delay of 1 to 3
  • a[1:3] is a vector bit 1 to 3. Thus, if

bit[0:15] a;
bit[0:2]  c;
c <=  a[1:3]; // "c" get vector slice of "a"

Again, sudy the SystemVerilog syntax!
Ben