SVA : Requirment : Trigger the assertion at particular time

SystemVerilog
,
1

HI ,

I have a requirement triggering assertion only at particular time.

Here is the picture uploaded.

Imgur: The magic of the Internet.

My assertion coding :

sequence ev_fusepullreq;
@(posedge side_clk iff oopi_sb_mnpput)
((oopi_sb_mpayload[7:0]==8’h40)##1
(oopi_sb_mpayload[7:0]==8’hd9)##1
(oopi_sb_mpayload[7:0]==8’hb8)##1
(oopi_sb_mpayload[7:0]==8’h80)##1
(oopi_sb_mpayload[7:0]==8’h00)##1
(oopi_sb_mpayload[7:0]==8’h16)##1
(oopi_sb_mpayload[7:0]==8’h00)##1
(oopi_sb_mpayload[7:0]==8’h00));
endsequence

My Sequence is asserting every “posedge side_clk and iff oopi_sb_mnpput”.I need the sequence should assert once at oopi_sb_mpayload[7:0]==8’h40 and check the transition until oopi_sb_mpayload[7:0]==8’h00 as per the assertion coded above.

Right now, As you can see in the waveform picture,assertion triggers every time when posedge side_clk iff oopi_sb_mnpput, and oopi_sb_mpayload[7:0] for other values.

I would like to know how to filter triggering the sequence.

-Regards,
-Raja.

2

What you have is a sequence; I assume that you are talking about an assertion of that sequence.
The link to the image is incorrect. What I think you want though is something like:


ap_1: assert property(
  @(posedge side_clk iff oopi_sb_mnpput)
    (oopi_sb_mpayload[7:0]==8'h40)|-> ##1  // Note the implication operator 
        (oopi_sb_mpayload[7:0]==8'hd9)##1
        (oopi_sb_mpayload[7:0]==8'hb8)##1
        (oopi_sb_mpayload[7:0]==8'h80)##1
        (oopi_sb_mpayload[7:0]==8'h00)##1
        (oopi_sb_mpayload[7:0]==8'h16)##1
        (oopi_sb_mpayload[7:0]==8'h00)##1
        (oopi_sb_mpayload[7:0]==8'h00)
);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115