Hi, I have hooked up the following assertion to an arbiter property p_req_to_grant(clk,rst,req,gnt); @(posedge clk) disable iff (rst) req |-> ##[0:$] gnt; endproperty ap_req_to_grant_0 : assert property(p_req_to_grant(clk,ares,req[0],grant[0])); Basically I just want to check that a grant sh…

In reply to ben@SystemVerilog.us : I agree about ‘strong’ qualifier. Also, there can be usage of ‘s_eventually’ over here. assert property (@(posedge clk) req |-> s_eventually gnt); Refer to this PDF for more alternatives.

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SVA : Property is a tautology

SystemVerilog

nimitz_class March 30, 2021, 7:29am 10

In reply to ben@SystemVerilog.us:

This solution is giving me UE results when req and gnt are high?