Verification Academy
SVA : Property is a tautology
SystemVerilog
SystemVerilog
,
Assertion-Based-Verification
,
SVA-Assertion
,
SVA
,
SVA-Arbiter
nimitz_class
March 30, 2021, 7:29am
10
In reply to
ben@SystemVerilog.us
:
This solution is giving me UE results when req and gnt are high?
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