SVA: Package for dynamic and range delays and repeats

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Hi Ben,

Can this be used for formal verification as well? I see questa propcheck throwing some errors on this.

***# Warning : Unsupported variable delay between local variable assign and read or within AND/OR/first_match/within constructs. Outside supported local variable synthesis subset. Local variable q_dynamic_repeat_v[0].

Thanks & Regards
Singhal R