SVA: Package for dynamic and range delays and repeats

SystemVerilog
,
3

Move the imports after the module name. For example

 
module top; 
    timeunit 1ns;     timeprecision 100ps;  
    import uvm_pkg::*; `include "uvm_macros.svh" 
    import sva_delay_repeat_range_pkg::*;
    bit clk, a, b, c=1, w;  
....