In reply to ben@SystemVerilog.us:
I need update in below assertion to make sure I check properly:
// 1.when req asserted I should check for valid that needs to be get asserted within 500clocks,
// then ack should get asserted IN THE NEXT CYCLE.
ap_req_valid: assert property(@ (posedge clk) $rose(req) |->
first_match(##[1:500] valid) ##[1:200000] ack);
How can I modify the above assertion to make sure valid between req and ack always asserted?
If req asserted followed by ack asserted and no valid asserted means an Error.
In the above check, it is checking for req first and if valid asserted then checking for ack.
In another way I want to check for valid must exist in between req and ack.