In reply to ben@SystemVerilog.us:
Hello Ben,
Sorry for mixing up the requirement in SVA and English description.
Now I will explain my requirement:
1.when clkreq asserted I should check for valid which needs to be get asserted within 500clocks, then clkack should get asserted.
2.If force_on asserted then validmust be asserted then force_on_ack must be asserted followed by force_on deassert, valid deassert, force_on_ack deassert.
3.In second case when force_on asserted it will check for valid, If valid already asserted due to clkreq it should go ahead and check for force_on_ack assertion followed we need to check for force_on deassertion and force_on_ack deassertion.
Thank you for your help…I tried to make all logic in single property but which is leading to nomatch case evethough signals are getting toggled.