SVA Issue

SystemVerilog
,
1

Hey,

I have the following scenario:

scenario image

One valid transaction is considered when VALID & RDY are both high.
Specification states that EOL must be 1 valid transaction wide.
That is, the fall of EOL can only occur when VALID & RDY are both high.
How can I write an assertion for it?
I was able to solve it with an initial-begin block but, it’s not elegant.
The assertions I tried writing doesn’t catch that.

Thanks in advance.

2

In reply to nnn314:

I would have liked to see your code. Anyway,


// the fall of EOL can only occur when VALID & RDY are both high.
ap_v2eol:  assert property(@posedge clk) valid && rdy |=> eol);

Ben Cohen
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