[SVA] How to write assertion including all below requirements in single assertion

SystemVerilog
,
4

In reply to BhaRath@Intel:

I had updated my checker as below, Now I can see assertion is failing at least.

But it is failing immediately after req asserted and it is failing in the next clock where it is finding ack asserted.

$rose(req) |-> ($rose(ack),cnt=0) ##1 (stable(ack) && cnt<200,cnt+=1) ##[0:] req[->1] ##1 (!ack && !req) ;

actually, 1.my expectation is to make sure ack is stable until req is high.
2. ack should be asserted once req asserted within specific clocks.