[SVA] How to write assertion including all below requirements in single assertion

SystemVerilog
,
3

In reply to Nishikant Tayde:
Hi Nishikant,

Good try…

I had tried your code but ended up with below compilation error:

**Error-[SVATHTLHS] Temporal LHS of ‘throughout’ operator.
stability_chk.sv, 5
A temporal LHS is not allowed with the ‘throughout’ operator.
Expression: (( ##[1:250] ack) ##1 ack throughout req ##1 ((!ack) && (!req)))

Please correct and try again.**

I had updated the code and ran like below,



module stability_chk;

  logic clk,rst,req=0,ack=0;

        property assert_chk1(req,ack);
          @(posedge clk)
          $rose(req) |-> ##[1:250] ack ##1 ($stable(ack) throughout (req[->1])) ##1 (!ack && !req) ;
            //$rose(req) |-> ##[1:250] ack ##1 ack throughout req ##1 (!ack && !req) ;
            //$rose(req) |-> ##[1:250] ack ##1 ack throughout req ##1 !ack && !req ;
        endproperty
      STABILITY_CHK:assert property (@(posedge clk) disable iff(rst)    assert_chk1(req,ack));


  initial begin
    clk=0;
    forever #5 clk=~clk;
  end
  initial begin
   #10 req=1; 
   #5 ack=1;
   #50 req=0; ack=0;
   #100;
   $finish;
  end
endmodule

Now I see assertion is shown as “No Match”. Please help me to resolve this issue.

Regards
Bharath