Hi,
What’s the best way to write an SVA for connectivity between top signal which is connected to internal dut module, for eg. If I drive pin s2p_in at the TB top, it will be reaching at test_bench.dut.u_top.u_chip_top.u_s2p.s2p_in?
Bind is way to do, but the top signals should be interface controllable?
Regards
Syed
ben2
March 1, 2017, 5:08pm
2
In reply to syed taahir ahmed :
Shouldn’t you bind the verification module or checker to the lowest level of the chain, i.e., the dut, i.e., u_s2p in your example?
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us :
In reply to syed taahir ahmed :
Shouldn’t you bind the verification module or checker to the lowest level of the chain, i.e., the dut, i.e., u_s2p in your example?
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
I see your point, I saw your checker explanation link but the dut RTL is deep inside the top module, so not sure how to use checker.
Regards,
Taahir
ben2
March 2, 2017, 7:22pm
4
In reply to syed taahir ahmed :
The following code demonstrates the concepts. It compiled and simulated.
import uvm_pkg::*; `include "uvm_macros.svh"
module m0(input bit clk, logic a);
bit m0b;
always @(posedge clk)
if (!randomize(m0b)) `uvm_error("MYERR", "This is a randomize error")
endmodule
module m1(input bit clk, logic b);
bit m1c;
always @(posedge clk)
if (!randomize(m1c)) `uvm_error("MYERR", "This is a randomize error")
m0 m0_i1(.cl k(clk), .a(b));
endmodule
module c_chk(input bit clk, input logic a, b);
ap: assert property(@(posedge clk) a |=> b);
endmodule
module top;
bit clk;
logic a, b,c ;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
m1 m1_i1(.clk(clk), .b(b));
initial begin
repeat(200) begin
@(posedge clk);
#1 if (!randomize(a, b, c)) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
/* bind_directive4 ::=
bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
| bind bind_target_instance bind_instantiation ;
bind_target_scope ::=
module_identifier
| interface_identifier
bind_target_instance ::=
hierarchical_identifier constant_bit_select
bind_target_instance_list ::=
bind_target_instance { , bind_target_instance } */
bind top.m1_i1.m0_i1 c_chk c_chk1(.clk(clk), .a(a), .b(m0b));
endmodule
// simulation
** Error: Assertion error.
# Time: 170 ns Started: 150 ns Scope: top.m1_i1.m0_i1.c_chk1.ap File: bind.sv Line: 17 Expr: b
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us :
In reply to syed taahir ahmed :
The following code demonstrates the concepts. It compiled and simulated.
import uvm_pkg::*; `include "uvm_macros.svh"
module m0(input bit clk, logic a);
bit m0b;
always @(posedge clk)
if (!randomize(m0b)) `uvm_error("MYERR", "This is a randomize error")
endmodule
module m1(input bit clk, logic b);
bit m1c;
always @(posedge clk)
if (!randomize(m1c)) `uvm_error("MYERR", "This is a randomize error")
m0 m0_i1(.cl k(clk), .a(b));
endmodule
module c_chk(input bit clk, input logic a, b);
ap: assert property(@(posedge clk) a |=> b);
endmodule
module top;
bit clk;
logic a, b,c ;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
m1 m1_i1(.clk(clk), .b(b));
initial begin
repeat(200) begin
@(posedge clk);
#1 if (!randomize(a, b, c)) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
/* bind_directive4 ::=
bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
| bind bind_target_instance bind_instantiation ;
bind_target_scope ::=
module_identifier
| interface_identifier
bind_target_instance ::=
hierarchical_identifier constant_bit_select
bind_target_instance_list ::=
bind_target_instance { , bind_target_instance } */
bind top.m1_i1.m0_i1 c_chk c_chk1(.clk(clk), .a(a), .b(m0b));
endmodule
// simulation
** Error: Assertion error.
# Time: 170 ns Started: 150 ns Scope: top.m1_i1.m0_i1.c_chk1.ap File: bind.sv Line: 17 Expr: b
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
Yes I am looking for this Construct, Thanks Ben.
Also I would like to see the assertions defined in macro.
Regards
Taahir
In reply to ben@SystemVerilog.us :
In reply to syed taahir ahmed :
The following code demonstrates the concepts. It compiled and simulated.
import uvm_pkg::*; `include "uvm_macros.svh"
module m0(input bit clk, logic a);
bit m0b;
always @(posedge clk)
if (!randomize(m0b)) `uvm_error("MYERR", "This is a randomize error")
endmodule
module m1(input bit clk, logic b);
bit m1c;
always @(posedge clk)
if (!randomize(m1c)) `uvm_error("MYERR", "This is a randomize error")
m0 m0_i1(.cl k(clk), .a(b));
endmodule
module c_chk(input bit clk, input logic a, b);
ap: assert property(@(posedge clk) a |=> b);
endmodule
module top;
bit clk;
logic a, b,c ;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
m1 m1_i1(.clk(clk), .b(b));
initial begin
repeat(200) begin
@(posedge clk);
#1 if (!randomize(a, b, c)) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
/* bind_directive4 ::=
bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
| bind bind_target_instance bind_instantiation ;
bind_target_scope ::=
module_identifier
| interface_identifier
bind_target_instance ::=
hierarchical_identifier constant_bit_select
bind_target_instance_list ::=
bind_target_instance { , bind_target_instance } */
bind top.m1_i1.m0_i1 c_chk c_chk1(.clk(clk), .a(a), .b(m0b));
endmodule
// simulation
** Error: Assertion error.
# Time: 170 ns Started: 150 ns Scope: top.m1_i1.m0_i1.c_chk1.ap File: bind.sv Line: 17 Expr: b
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
Yes I am looking for this Construct, Thanks Ben.
Also I would like to see the assertions defined in macro.
Regards
Taahir