SVA for checking fairness of Round-Robin Arbiter

SystemVerilog
, ,
5

In reply to imajeeth:

Need Input !!

I have used following code to verify round robin arbitrator using SystemVerilog Assertions, can anyone of you correct me if I’m wrong, or kindly share if you have an efficient code than the following, thank you!!
I’m particularly looking for a long/lengthy chain of requests/grant

here gnt = Grant of length 16
req = Request of length 16

generate
  for (genvar i = 0; i<16; i++)
    for (genvar j=i+1; j!=i; j++)
      begin
        if(j==16) 
          j=0;
        assert property
        (
          @posedge clk
          (gnt[i] && req[j]) |=> (gnt[j] && !req[i]) 
        )
      end
endgenerate

// Below code is to make sure only one gnt is high at any point of time

assert property 
  ( 
    @posedge (clk)
    $onehot(gnt) ==1;
  )