Why SystemVerilog assertions are evaluated in observed region, although the values are sampled in preponed region ?

In reply to Harshit : Why SystemVerilog assertions are evaluated in observed region, although the values are sampled in preponed region ? Keep in mind that SystemVerilog must emulate concurrency using a sequencial non-concurret processing computer. Before getting into an example that explains th…

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samirxd September 7, 2021, 7:18am 7

In reply to ben@SystemVerilog.us:

Thanks Ben.