In reply to samirxd:
In reply to ben@SystemVerilog.us:
Can you explain why “%t sampled q=%d, current q=%d, past q=%d, var w=%d” is getting printed before “%t sampled q=%d, current q=%d, past q=%d, var y=%d” although it has ##0 delay ?
NO, but I believe it is how the tool handles the printing.
I tried the model at Edit code - EDA Playground
got what you expected, the “y” print before the “w” print
# 210 sampled q= 30, current q= 30, past q= 27, var y= 30
# 210 sampled q= 30, current q= 30, past q= 27, var w= 10
# 250 sampled q= 25, current q= 25, past q= 9, var y= 25
# 250 sampled q= 25, current q= 25, past q= 9, var w= 2q
In assertion the $display will get evaluated in active region or re-active region?
- In immediate assertions, the $display is evaluated at the point in the procedural process they appear. Thus,
module m;
bit a, b, d, clk;
always_comb begin
a_ab: assert(a==b) else $display("%t a=%b, b=%b", $realtime, a, b);
// $display is evaluated in the Active Region.
end
- Concurrent assertion
property p;
bit v;
(a, v=d) |-> ##1
(v, $display("%t EVALUATED IN OBSERVED REGION a=%b, b=%b", $realtime, a, b)) ##0 b;
endproperty
ap_p: assert property(@(posedge clk) p) else $display("%t ACTION BLOCK IN RACTIVE REGION : a=%b, b=%b", $realtime, a, b);