SVA: dma req check

SystemVerilog
3

In reply to :

Hi Ben,

    Thanks for suggestion , i have written two kinds of checks as below



module test;
  bit clk,dma_req,dma_burstend;
   always #5 clk=~clk;
   property dma_req_check;
      @(posedge clk)
	$rose(dma_req)|-> (dma_req[*2] ##1 !dma_req);
   endproperty

   ap_dma2cycles1: assert property (dma_req_check);

   property dma_req_check2;
      real t,t_now;
      real t2=20;
      @(posedge dma_req) (1,t=$realtime) |-> @(negedge dma_req)(1,t_now=$realtime) ##0 ((t_now-t)==20);
   endproperty
       
  ap_dma2cycles2:assert property(dma_req_check2);

   initial
     begin
	#5;
        dma_req=1;
	#25;
	dma_req=0;
	#30;
	$finish;
    end
endmodule // test

After the simulation ,i am expecting that both assertion should fail, but ap_dma2cycles2 catching the failure where as ap_dma2cycles1 is not.

in ap_dma2cycles1 : assertion started executing from 2nd clock cycle.