SVA: Counting and Comparing

SystemVerilog
, ,
2

In reply to sonofthesand:
The easiest solution is to use plain SystemVerilog code, as shown below:
and in Edit code - EDA Playground

// import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
	bit clk, a, b, go, done;  // go and done are single pulses
	int acnt, bcnt, stats;
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;  
	
	initial begin // signal generator 
		repeat(30) begin 
			@(posedge clk) go <= 1'b1; 
			@(posedge clk) go <= 1'b0; 
			repeat(27) @(posedge clk); 
			done <= 1'b1;
			@(posedge clk) done <=1'b0;
		end 
	end 	
	// verification ode 
	always_ff  @(posedge clk)  begin :ctab
		static int cta;
		static int ctb;
      if(go) begin cta=0; ctb=0; end 
		if(done) begin 
			$display("t=%t, cta=%d, ctb=%d", $time, cta, ctb);
          dostats(cta, ctb);
		end
      if(a) begin cta=cta+1'b1; end
      if(b) begin ctb=ctb+1'b1; end
	end 	
 
	
	function void dostats (int x, y); 
		 acnt=x; 
		 bcnt=y;
		 stats= 100*x/y;
      $display("@t= %t, acnt=%d, bcnt=%d, stats=%d percent", $time, acnt, bcnt, stats); 
	endfunction : dostats
	
	initial begin // signal generator
		repeat(1200) begin 
			@(posedge clk);   
			#1 if (!randomize(a, b)  with 
					{ a dist {1'b1:=1, 1'b0:=3};
					b dist {1'b1:=1, 1'b0:=2};
                    });
					end 
					$stop; 
		end 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us