In reply to ben@SystemVerilog.us:
In reply to Adarsh Santhosh:
Looks OK
// Assertion states that in the cyce following done, and thereafter the done, a==0 until end of sim
initial ap_preferred: assert property(@(posedge clk)
done[->1] |=> strong(!a[*1:$]));
I had some follow up questions.
What if there can be a delay in “a” going low after done.
a can be “0” in next cycle or any of the upcoming cycles.
Will below work?
// Assertion states that in any of the cycles following done : "a" is low, and thereafter, a==0 until end of sim
initial ap_preferred: assert property(@(posedge clk)
done[->1] |=> strong( !a[->1] ##1 !a[*0:$]));
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