In reply to ben@SystemVerilog.us:
thanks, Ben for the detailed explanation. It works.
One more doubt.
Lets say during the “end/done” section, signal “a” is “0” and i wanted to check if it says low for rest of the sim.
Would below work or do u suspect any issues?
initial ap_preferred: assert property(@(posedge clk)
done[->1] |=> strong(!a[*1:$]));
thx