In reply to ben@SystemVerilog.us:
From LRM:
Ranged form of strong always
s_always [ constant_range ] property_expr
A property s_always [constant_range] property_expr evaluates to true if, and only if, all current
or future clock ticks specified by constant_range exist and property_expr holds at each of these
clock ticks. The range for a strong always shall be bounded
From my sim, it looks like if the range doesnt exist, it will fail.