SVA: condition met between two disabled sections not showing pass/finish

SystemVerilog
,
14

In reply to Adarsh Santhosh:
The strong qualifier applies to a sequence that is a property.
That makes the property strong.

below works

module m;
  bit clk, done, a;
  initial 
    ap_1: assert property(@(posedge clk) 
                          done[->1] |=> (!a[->1]) 
                          #=# s_always[1:100000] !a);
endmodule