SVA: Clock Alignment

[moogyd]

Hi,
From our system clock, we generate a number of divided clocks with non 50/50 duty cycle

clk_root ||||||||||||_
clk_div2 ||||___||
clk_div4 ___||

I need an assertion to ensure that clk_div4 is aligned with clk_div2. Something like: @(posedge clk_div4) |-> @(posedge clk_div2)

I currently have:

  // Do we beed to handle clk_div2 being SA1?
  // No - this should be checked elsewhere
  always_comb
    if (clk_div4)
      AS_clk_div4_in_phase_clk_div2: assert #0 (clk_div2) ;

It seems to work, but I was hoping for something a little “nicer”. Any suggestions.
Thanks,
Steven

[ben2]

In reply to moogyd:

Looks like a good solution. The always_comb if (clk_div4) triggers on a change in clk_div4 going to a 1’b1, and the deferred assertion reporting is done in the Reactive Region with the #0, or in the Postponed Region with the final. In your case, either version of the deferred assertion looks OK, unless you have tricky combinational logic for the generation of clk_div2, which I doubt.

1800’2012: The processing of the action block differs between
observed and final deferred assertions as follows:
— For an observed deferred assertion, the subroutine shall be scheduled in the Reactive region. Actual argument expressions that are passed by reference use or assign the current values of the underlying variables in the Reactive region.
— For a final deferred assertion, the subroutine shall be scheduled in the Postponed region. Actual argument expressions that are passed by reference use the current values of the underlying variables in the Postponed region.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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[moogyd]

In reply to ben@SystemVerilog.us:

Thanks Ben!
Steven