In reply to ssureshg_:
Keep in mind that the send 16x clk and the receive 16x clk are not synchronous to each other, though at same frequency. I would write the sequence as
(1’b1 ##2 $stable(tx_rx)[*12] ##2 1’b1)[*20];
Ben Ben@systemverilog.us
In reply to ssureshg_:
Keep in mind that the send 16x clk and the receive 16x clk are not synchronous to each other, though at same frequency. I would write the sequence as
(1’b1 ##2 $stable(tx_rx)[*12] ##2 1’b1)[*20];
Ben Ben@systemverilog.us