In reply to Mohamed_TN:
In reply to ben@SystemVerilog.us:
In this way the assertion will check B in each cycle in the window, consider the case when A is triggered by only one B event during the window [1:20].
Again, this assertion is far better, and is more expressive
p1: assert property(@(posedge clk)
b |-> ##[1:20] a); // better
With the generate, you end up with 20 separate assertions, one or more of which may succeed if b was true at 1 or more previous cycles, and the others will fail.
There is no $past with a range.
The $past function provides the sampled value that an expression held in a previous nth cycle. The syntax of the function is: [1]
$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])
generate for (genvar i=1; i<=20; i++)
p1: assert property(@(posedge clk)
a |-> $past(b, i));
endgenerate
The nature of the beast!
Ben Cohen
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf