SV virtual interface array

UVM
,
1

Hey all; I hope you’re all doing good.
My DUT (wrriten in vhdl) has 3 interfaces of the same bus protocol “pro”.
I have pro_itf interface


interface pro_itf 
bit [5:0] a;
bit [5:0] b;
endinterface

then a container of that interface


interface arr_pro_itf
pro_itf pro_itf_array[2]; 
endinterface

In uvm tb_top module
i intstantiated the container


module top
arr_pro_itf arr_pro_vitf;
dut dut_i();
//to map dut signals to my sv interfaces I did as follows
genvar idx;
generate
for(idx=0;idx<=itf_num;idx++) begin
arr_pro_vitf.pro_itf_array[idx].a=assign dut_i.a[idx];
end
endgenerate

The compiler prints me an error about indexing (idx)

2

In reply to abdelaali_21:

It always helps to shoe the exact error message and point to the line where it is coming from.
There are a number of syntax errors in your code and there are no virtual interfaces, but I think this might be what you intended.

interface pro_itf;
  bit [5:0] a;
  bit [5:0] b;
endinterface

interface arr_pro_itf;
  pro_itf pro_itf_array[2](); 
endinterface
module dut;
  bit [5:0] a[2];
endmodule
module top;
  arr_pro_itf arr_pro_vitf();
  dut dut_i();

  for(genvar idx=0;idx< 2;idx++) 
     assign arr_pro_vitf.pro_itf_array[idx].a=dut_i.a[idx];

endmodule