I need to write a SystemVerilog stimulus generator for a real number model of an RLC tank circuit. The stimulus generator outputs must have data type real, but also need to be tristate capable. That is, the datatype of the outputs must include real values plus ‘z’. Is there a ‘best practice’ way of doing this?
I tried using a logic data type on the outputs, and it works very well. When the outputs are driven to z, the tank circuit exhibits damped oscillation as expected, with no loading from the stimulus generator. However, with real data type on the outputs, there is no ‘z’ value that can be generated, and the tank circuit does not oscillate, due to ‘loading’ by the stimulus generator.
You need to be more specific about what this real value represents. Typically people use a voltage, current, resistance (VIR) triad to represent a signal and there’s no need for separate Z state.
The real-valued output is the value of voltage applied to one of the tank ports. The other port is driven with the complementary voltage. That is, the two tank ports are driven with either 3V, 0V or 0V, 3V on the two ports. The z value will model the case when the tank is disconnected from any voltage, and responds with a decaying sine wave until it fully discharges.
I know about the (V,I,R) triad, and will use that method if no other method can be identified. But it seems like more work than needed. For example, can I just use a force to z when I want to tristate the ports?
The real data type does not support X and Z states. Those states only apply to integral types.
Only nets can be driven from multiple sources. And built-in nets only support integral types. You would have to use a user-defined nettype, or one provided by your tool vendor.
THanks Dave for your help. I’ll investigate UDNs. From my analog/mxs perspective there is a significant need for this – we frequently encounter designs with real signals that need to tristate occasionally.