SV standard (1800-2012) - section 11.4.14.3 - need clarification in streaming example

SystemVerilog
,
1

Hi,

Am I misreading this?
{>>{ a, b, c }} = 23’b1; // error: too few bits in stream
{>>{ a, b, c }} = 96’b1; // OK: unpack a = 0, b = 0, c = 1
{>>{ a, b, c }} = 100’b1; // OK: unpack as above (4 bits unread)

I expect the third one to produce a = 0, b = 0, c = 0. And testing with Cadence Incisive, that is what I get. Can someone please clarify if the standard is indicating that this should be a = 0, b = 0, c = 1?

Thanks,
Nachum

2

In reply to nachumk:

int ： 32bit default

a:[99:68] bit -->0
b:[67:36] bit -->0
c:[35: 4] bit -->0
[3:0] bit unused