SV Regex Bracket Match

SystemVerilog
,
1

I am trying to create a simple pattern match using regex in SV. I see that its not able to match it although the regex looks right. I tested it out in

module top;
  string s = "test[0]";
  
  initial begin
    if(s.match(".*[\d].*") ) $display("MATCH");
    else $display("NOMATCH");
  end
endmodule

Other things that should ideally work but its still no match:

".*\[.\].*"
".*\[.*\].*"

The only thing that I see working is:

".*[0].*"

What if I want to match any number inside the “”?

2

In reply to ritz91:



module top;
  string s = "test[0]";
  
  initial begin
    if(s.match(".*[\\d].*") ) $display("MATCH");
    else $display("NOMATCH");
  end
endmodule
3

In reply to rag123:

Thank you! Now I think it matches everything

string s = “test[0123]”;

It should be “\d+” may be to match “0123”.