In which part of the System verilog verification environment should I provide the assertions and coverage checks?
In reply to Muthamizh:
Different verification environments have different parts. In the UVM, there are coverage collector classes derived from uvm_subscriber. Protocol assertions typically go into interfaces.
In reply to dave_59:
I am trying to do the complete testbench for fsm sequence detector. So in this where could i do the coverage checks and assertions?
In reply to Muthamizh:
Also what could be the scoreboard check for 1001 sequence detector? How to write? Could you please help me out? Tell me the gist and i will try to code it.