SV Probability Constraint Question

SystemVerilog
,
1

Trying to solve a question : For a 8 bit variable if the past randomization resulted in a odd value, the next randomization should be even with 75% probability else be even with 25% probability. Write a constraint. Does my solution below seems correct?

class sample;
  static bit[7:0] prev_data;
  rand bit[7:0] data, temp_data_even, temp_data_odd;
  rand bit odd;
  rand bit even;
  
  constraint c{
  temp_data_even%2  == 0;
  temp_data_odd%2 == 1;
    
    (prev_data%2==1) -> data dist {temp_data_even := 75, temp_data_odd :=25};
    (prev_data%2==0) -> data dist {temp_data_even := 25, temp_data_odd :=75};
    
  }
  
  function void post_randomize();
    prev_data = data;
  endfunction
endclass


module tb;
  sample s = new();
  
  initial begin
    repeat(10) begin
    s.randomize();
      $display("%d",s.data);
    end
  end
endmodule
2

In reply to totochan1985:

You can check your constraints by adding 4 counters in post_randomize. Then you will see there is no need for the extra temp_data_even/odd variables.

Also, there is no need to declare prev_data as a static property.

3

In reply to dave_59:

It is mostly same as what you have with one change - not having the temp data

class packet;
  rand bit[7:0] data;
  bit[7:0] prev_data;
  constraint c_probability {
    //odd -> next should be even with 75% probability
    if(prev_data%2 == 1 && prev_data != 0) (data%2 == 0) dist { 1 := 75, 0:= 25};
    //even -> next should be even with 25% probability
    else (data%2 == 0 && prev_data != 0) dist { 1 := 25, 0:= 75};
  }
  
  function void post_randomize();
    prev_data = data;
  endfunction
endclass
module top;
  initial begin 
    packet p = new;
    repeat(10) begin 
      p.randomize();
      $display("%0d",p.data);
    end
  end 
endmodule