[SV LRM 2017] formal argument passed by reference

SystemVerilog
,
1

As per LRM sec. 9.3.2

Within a fork-join_any or fork-join_none block, it shall be illegal to refer to formal arguments passed by reference other than in the initialization value expressions of variables declared in a
block_item_declaration of the fork.

module abc;
  
initial
  for( int j = 1; j <= 3; ++j )
    fork
      automatic int k = j; // local copy, k, for each value of j
      #j $write( "%0d", j);
    join_none
 
endmodule

In code above, does j refers to formal argument? If NO, then please provide example with same.

2

In reply to juhi_p:

You need to be inside a task or function to have a formal argument.

module abc;
  
initial
  for( int actual_arg = 1; actual_arg <= 3; ++actual_arg )
    do_this(actual_arg);

task automatic do_this(ref int formal_arg);
    fork
      int k = formal_arg; 
      #k $write( "%0d", k);
    join_none
endtask
endmodule

Note that defining do_this() as below would have the same behavior as above since each invocation of the task has a local copy of k.

task automatic do_this(input int k);
    fork
      #k $write( "%0d", k);
    join_none
endtask