Sv fixed array

SystemVerilog
,
1

Can anyone help me to solve my doubt,Why in array2 takes values takes a[5]=0,as array1 takes value array1[5]=5

module fixedsize_array;

int array1[6];
int array2[5:0];

initial begin
array1 = '{0,1,2,3,4,5};
array2 = '{0,1,2,3,4,5};

foreach(array1[i]) $display("\t array1[%0d] = %0d",i,array1[i]);

$display("-------displaying array2-------");
foreach(array2[i]) $display("\t array2[%0d] = %0d",i,array2[i]);

// for(int i=0;i<6;i++) $display(“\t array2[%0d] = %0d”,i,array2[i]);

end
endmodule

     array1[0] = 0
 array1[1] = 1
 array1[2] = 2
 array1[3] = 3
 array1[4] = 4
 array1[5] = 5

-------displaying array2-------
array2[5] = 0
array2[4] = 1
array2[3] = 2
array2[2] = 3
array2[1] = 4
array2[0] = 5

2

hi vlsique ,

please refer this ,
module asd;
int array1[6]; // in this array by default it starts from 0
int array2[5:0]; // in array2 it starts from MSB , here msb bit is 5
int array3[0:5]; // in array3 it starts from MSB , here MSB bit is 0 && i think there is no differnce between array1 and array3

initial begin
array1 = '{0,1,2,3,4,5};
array2 = '{0,1,2,3,4,5};
array3 = '{0,1,2,3,4,5};

foreach(array1[i]) $display(“\t array1[%0d] = %0d”,i,array1[i]);

$display(“-------displaying array2-------”);
foreach(array2[i]) $display(“\t array2[%0d] = %0d”,i,array2[i]);
// for(int i=0;i<6;i++) $display(“\t array2[%0d] = %0d”,i,array2[i]);
$display(“-------displaying array3-------”);
foreach(array3[i]) $display(“\t array3[%0d] = %0d”,i,array3[i]);

end
endmodule

output :
array1[0] = 0
array1[1] = 1
array1[2] = 2
array1[3] = 3
array1[4] = 4
array1[5] = 5
-------displaying array2-------
array2[5] = 0
array2[4] = 1
array2[3] = 2
array2[2] = 3
array2[1] = 4
array2[0] = 5
-------displaying array3-------
array3[0] = 0
array3[1] = 1
array3[2] = 2
array3[3] = 3
array3[4] = 4
array3[5] = 5

this ans is not satisfy , sorry
thank you
samy

3

In reply to samy:

Thanks