SV Error

SystemVerilog
1

Hi Team,

there is some simulation error for my SV code,
can you look in to this

Thanks,

2

In reply to PJ:

You have syntax errors and the messages are clear what the problem is. Have you read them?

3

In reply to dave_59:

Hi,
I tried for remove an errors,But i did not solve them, can you help on that?