SV cross coverage with 'intersect' keyword

SystemVerilog
,
6

cp_data is defined with option.auto_bin_max = 1, it creates a single bin covering all possible values of data. The expression binsof(cp_data) intersect {'h0} does not restrict the bin to only data = 0 but it simply checks if the universal bin includes 0 (which it always does). As a result, all cross bins effectively match whenever addr = 'h100 and wr = 1, regardless of the actual data value. so the correct option would be to define explicit bins for data value. Defining bins(just like below) will resolve the issue.

    cp_data : coverpoint data {
      bins band = {'h0};  // Explicit bin for data=0
      bins khula1 = {'h1};  // Explicit bin for data=1
      bins khula2 = {'h2};  // Explicit bin for data=2
      option.weight = 0;
    }