SV contraint to repeat elements n time

SystemVerilog
,
6

I have a follow-up question . I notice that following code in procedural block ( like initial block ) works fine and give same result ::


bit [3:0] b [$] = '{ 1 , 6 , 2 , 1 , 9 , 1  , 2 , 10 , 15 } ;
int b1 ;

initial begin

b1 = b.sum() with ( ( item == 1 ) ? item : 0  ) ;

$display(" b is %0p",b);

$display(" Result of b.sum() with ( ( item == 1 ) ? item : 0  ) is %0d ",b.sum() with ( ( item == 1 ) ? item : 0  ));

$display(" Result of b.sum() with ( ( item == 1 ) ? 1 : 0  ) is %0d ",b.sum() with ( ( item == 1 ) ? 1 : 0  ));

$display(" Result of b.sum() with ( ( item == 1 ) ? ( item == 1 ) : 0  ) is %0d ",b.sum() with ( ( item == 1 ) ? ( item == 1)  : 0  ));

end

Whereas if I try it in a Constraint all 3 of the variation fails ::


    // TYPE 1 
a.sum() with ((item == 1) ? item == 1 : 0 ) == 10 ;
a.sum() with ((item == 2) ? item == 2 : 0 ) == 5 ;
a.sum() with ((item == 3) ? item == 3 : 0 ) == 5 ;
                                                    
    // TYPE 2 
a.sum() with ((item == 1) ? item : 0 ) == 10 ;
a.sum() with ((item == 2) ? item : 0 ) == 5 ;
a.sum() with ((item == 3) ? item : 0 ) == 5 ;
                                                    
    // TYPE 3
a.sum() with ((item == 1) ? 1 : 0 ) == 10 ;
a.sum() with ((item == 2) ? 2 : 0 ) == 5 ;
a.sum() with ((item == 3) ? 3 : 0 ) == 5 ;