SV can' t read the type from VHDL

SystemVerilog
1

Hello there,

On my VHDL based design, I have the following package for my state machine:

package test_pkg is
   type t_state is (IDLE, MODE_1, MODE_2, POWERDOWN);
end package;

On my SV testbench,I imported the package:

import test_pkg::*;
t_state state;
assign state = `PATH_INSIDE_THE_VHDL_DESIGN.state;

Note that ‘state’ in PATH_INSIDE_THE_VHDL_DESIGN is defined as t_state and I’m trying to probe the ‘state’ from the SV testbench. Both the design and the testbench are compiled with the -mixedsvvh switch.

However, on modelsim I keep on getting this eror:
Illegal assignment to type ‘test_pkg__mti__sv_equi_implct_pack.enum bit[0:1]’ from type ‘design.enum bit [0:1]’ : An enum variable may obly be assigned the same enum typed variable or one of its values.

Can anyone shed some light why modelsim identify the same type as two types ?

2

This should work if you have the latest version of Questa. Otherwise you need to contact Mentor support.

3

In reply to dave_59:

Hi Dave,

Indeed, it didn’t work on questa 10.1c, but works with 10.2c_1.

thanks