In reply to dave_59:
Hello Dave,
May be I have not understood the bind construct that well. Could you please show me through an example (possibly using the FIFO example I have used above) as to how I could do this?
Please note that in my example above, dut_top_level, sub_component, sub_sub_component and fifo are all Verilog modules. There is a top level SystemVerilog testbench module named top_level_tb which instantiates dut_top_level and where I would want to instantiate the module containing assertions for FIFO named fifo_assertions. So, the hierarchy in terms of top level testbench would be something like this:
top_level_tb.dut_top_level
top_level_tb.fifo_assertions
Thus, the FIFO signals are not directly accessible in the top level testbench. In such case, to access the FIFO signals in top level testbench (for each of the FIFO instances), won’t I have to use the hierarchical paths? Please correct me if I am wrong.
I would really appreciate if you provide me with an example.
Thanks!