SV assertion for verifying a sequence of events not working

SystemVerilog
4

In reply to ben@SystemVerilog.us:

Looks like its not working. I tried with goto operator just as you mentioned.

I tried forcing reg2 with 17’h1FFFF throughout the testmode high. Didnt fail, even though i had check for 17’h00000.
REG2 17’h1FFFF

Also, tried making c low when antecedent true. Didnt error out.
c low when antecedent true

But, it did error out when reg1 was 17’h0 instead of 17’hF.
reg1 17’h0

i tried using first match for antecednt as below. But, it didnt help my case.

    @(posedge clk) first_match(a && b) |-> (1, $display ("Checking SEQ1"))