SV assertion for clock gating & Reset check

SystemVerilog
8

In reply to S.P.Rajkumar.V:

property clk_gating_check_g_clk;
@posedge(ref_clk)
($fell(clk_en) ##[2:4] !g_clk) |-> (!g_clk throughout clk_en[->1]);
endproperty

Hi. I have question with your assertion about checking the clock gating.
I’m not so sure if it can catch any errors in clock gating. It’s because g_clk is in-phase with ref_clk, and the checking is done only at the positive edge of ref_clk.

So let’s say that clk_en fell but there’s a bug and g_clk still continues to toggle. Since ref_clk and g_clk are in-phase, and the checking is done in positive edge of ref_clk, then it will never catch g_clk as high. It always samples g_clk as low.

Did I understand it correctly?