In reply to ben@SystemVerilog.us:
Hi Ben,
Yes, the issue encountered is similar and the tools response is also correct.
After enabling the assertions for functional tests (written by other engineers), incomplete issue has occurred. It is expected, as the reset is released initially in all those tests once and then some data processing/manipulation will happen. The complete reset gating/ungating sequence will not be present in those test scenarios.
I’ll make use of initial at the moment for my reset/clock test scenarios.
Thank you very much for clarifying all my queries.
Regards,
Rajkumar.