SV assertion for clock gating & Reset check

SystemVerilog
6

In reply to S.P.Rajkumar.V:
If I understand you correctly, your test scenario looks as follows:


let k=5; // an example 
let n=2000; // another supposition
// $fell(reset_en) ##[1:n] reset_en ##[1:k] $fell(reset_en) ##[1:$] end_of_simulation
// In that case the assertion ap_reset is fired twice.
// It succeeds at the first firing with the sequence $fell(reset_en) ##[1:n] reset_en ##[1:k] 
// However the second firing never completes since there is no reset_n==1.
// That second sequence is $fell(reset_en) ##[1:$] end_of_simulation
ap_reset: assert property(@(posedge ref_clk)
    $fell(reset_en) |-> (reset_n[*1:$] ##1 reset_en)  within reset_en [->1]);
// So the tool gave you the correct response. 
// If you want to test this assertion once, you could put the assertion in an initial statement 
initial begin 
// Maybe some wait cycles ??
 ap_reset: assert property(@(posedge ref_clk)
    $fell(reset_en) |-> (reset_n[*1:$] ##1 reset_en)  within reset_en [->1]);
end

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us