In reply to ben@SystemVerilog.us:
Hi Ben,
Thank you. ‘within’ has perfectly worked in this scenario.
In the test scenario the above sequence has satisfied once and assertion has passed; and then the second time the test scenario stopped at reset release itself, there-by encountering an incomplete assertion issue at the end of simulation. The same issue can occur with all other previous assertions as well (since it all depends on stimulus).
I hope the only solution here is to re-code each assertion sequence above by splitting them into multiple parts (say for ex. one each for reset-assertion, de-assertion, and intermediate checks).
Could you just comment, if there is any other way to go-ahead with the existing code?
Regards,
Rajkumar.