In reply to ben@SystemVerilog.us:
Hi Ben,
Yes, this is the assertion I’m talking about. My requirement is:
I want to create a tolerance window few cycles AFTER clk_en has a 1->0 transition, as well as a few cycles BEFORE clk_en has a 0->1 transition.
In your example, the ##[2:4] is the tolerance window for few cycles after clk_en has a 1->0 transition($fell). That works perfectly fine.
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However, I also want to cover the case where clocks might start ticking few cycles before clk_en goes from 0->1. Your earlier assertion will fail in this case. How do we cover that case?
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If I want to create a tolerance window before and after 0-1> and 1->0 transition of clk_en, how do we go about that? The before and after is for each of the 2 transitions. So basically 4 windows: before 0->1, after 0->1, before 1->0, and after 1->0.
Hope that makes it clear.