SV assertion for clock gating & Reset check

SystemVerilog
17

In reply to imajeeth:

In reply to ben@SystemVerilog.us:
This assertion will fail for the following scenario, where clocks start toggling ‘n’ cycles before clk_en goes high. How would we add tolerance to this scenario?

I am not clear as to which assertion you are talking about. This one?

@(posedge ref_clk)
    ($fell(clk_en) ##[2:4] !g_clk) |-> 
              @(negedge ref_clk)(!g_clk throughout clk_en[->1]);

In any case, you can control the start and behavior on an assertion with supporting logic, like events. Please clarify your requirements.
Ben ben@systemverilog.us