My question is in continuation to the below link, but since that was alredy solved , i was not sure if i need to create new question.
https://verificationacademy.com/forums/systemverilog/sum-constraints
i am trying to do somewhat similar what is described above . In above example it is a queue is of local typedef.
In my case , cyclesq is an integer type queue. cyclesq.size() < tran_num & > 0. sum of the fields of this queue should be tran_num. and the fields of this queue should be positive numbers (item % 2 == 0).
Below is my code but i am not able to achieve the results.
for e.g.
cyclesq.size() is 10 , fields should be 2,4,2,2,2,0,0,0,0,0 or 2,4,4,0,0,0,0,0,0,0 or 8,2,0,0,0,0,0,0,0,0
``` verilog
module cycle_cnt();
class cycle_cnt #(int trans_num = 10);
int tran_num = trans_num;
rand int cyclesq[$];
constraint cyclesq_size {
cyclesq.size() <= tran_num;
cyclesq.size() > 0;
cyclesq.sum with (int'(item % 2 == 0)) == tran_num;
}
endclass
int cnt = 0;
cycle_cnt #(10) cycle_cnt_i;
initial begin
cycle_cnt_i = new();
assert(cycle_cnt_i.randomize());
$display(" for tran_num = %0d cyclesq size is %0d",
cycle_cnt_i.tran_num ,cycle_cnt_i.cyclesq.size() );
for(int i = 0 ; i < cycle_cnt_i.cyclesq.size() ; i ++) begin
cnt = cnt + cycle_cnt_i.cyclesq[i];
$display ("%d with cyclesq is %0d cycle_cnt is %0d ",
i,cycle_cnt_i.cyclesq[i],cnt);
end
end
endmodule