Suggestions for Setup time check via Concurrent Assertion

SystemVerilog
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1

I was trying to check for Setup and Hold time check via Concurrent Assertions .

I did manage to write one for hold time :: EDA_hold_time . This works as intended .
[ I observe that that PASS / FAIL action block isn’t triggered on posedge of clk . For Multi-Clocked property , they would be triggered on the last clock tick in the Consequent ( in my case it’s on change in the input Signal ]

I have 2 further questions ::

(1) How is it that the variable ’ a ’ get passed by reference ?
( Generally the variables are passed by value for subroutines and would need ’ ref ’ type declaration )

(2) Any suggestions for Setup time check ?

2

In reply to hisingh:

By default, sequence/property arguments are in-lined into their body just like a text macro with the restriction that actual arguments must be valid operands of a sequence/property. So Sig gets replaced by a within the property body.

For a setup check, you would swap @(Sig) with @(posedge clk).